STM32 Bootloader
Customizable Bootloader for STM32 microcontrollers
system_stm32l4xx.c File Reference

This file provides the CMSIS Cortex-M4 system initialization and clock configuration. Originally provided by ST. More...

#include "stm32l4xx.h"

Go to the source code of this file.

Macros

#define HSE_VALUE   8000000U
 
#define MSI_VALUE   4000000U
 
#define HSI_VALUE   16000000U
 

Functions

void SystemInit (void)
 Initialize the system before calling the main() function.
 
void SystemCoreClockUpdate (void)
 Update the SystemCoreClock variable according to the clock register values. More...
 

Variables

uint32_t SystemCoreClock = 4000000U
 Define to enable user-defined vector table address setting. More...
 
const uint8_t AHBPrescTable [16]
 
const uint8_t APBPrescTable [8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}
 
const uint32_t MSIRangeTable [12]
 

Detailed Description

This file provides the CMSIS Cortex-M4 system initialization and clock configuration. Originally provided by ST.

STM32 Bootloader

Author
Akos Pasztor

This file provides two functions and one global variable to be called from the user application:

  • SystemInit(): This function is called at startup just after reset and before jumping to the main program. This call is made inside the startup_stm32l4xx.s file.
  • SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the application to setup the SysTick timer or configure other parameters.
  • SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

After each device reset the MSI (4 MHz) is used as system clock source. Then SystemInit() function is called from the startup_stm32l4xx.s" file to configure the system clock before to jumping to the main program.

This file configures the system clock as follows:

Parameter Value
System Clock source MSI
SYSCLK (Hz) 4000000
HCLK (Hz) 4000000
AHB Prescaler 1
APB1 Prescaler 1
APB2 Prescaler 1
PLL_M 1
PLL_N 8
PLL_P 7
PLL_Q 2
PLL_R 2
PLLSAI1_P NA
PLLSAI1_Q NA
PLLSAI1_R NA
PLLSAI2_P NA
PLLSAI2_Q NA
PLLSAI2_R NA
Require 48MHz for USB OTG FS, SDIO and RNG Disabled

Definition in file system_stm32l4xx.c.